1. Field of the Invention
The present invention relates to a semiconductor memory device having a 2-transistor and 1-capacitor type memory cell, one type of a so-called gain cell, reading a storage data held in the cell, amplifying the same by a read transistor and reading it out onto a bit line.
2. Description of Related Art
In a dynamic random access memory (DRAM) for holding a signal voltage by the capacitance of a capacitor and storing information corresponding to the held signal voltage, memory cells have been miniaturized more and more along with the increasing capacity of recent years. The miniaturization of the memory cells has led to a reduction in the capacitance of the capacitor. As a result, the amplitude of a read signal has become small, so it is becoming difficult to secure stability of operation at a read operation and guarantee precision of the read data. For this reason, attention is being paid to a so-called gain cell for holding a signal voltage at the gate of the read transistor, amplifying the signal voltage by the read transistor at the read operation, and outputting the same to the bit line.
FIG. 21 is a circuit diagram of an example of the configuration of the 2-transistor and 1-capacitor type memory cell of one type of gain cell.
As illustrated, this memory cell is configured by a write transistor Q1, a read transistor Q2, and a capacitor C1. One electrode of the capacitor C1 is connected to a read word line RWL, while the other electrode is connected to a storage node SN. In the write transistor Q1, the gate is connected to a write word line WWL, the drain is connected to a write bit line WBL, and the source is connected to the storage node SN. In the read transistor Q2, the gate is connected to the storage node SN, the source is connected to a read bit line RBL, and the drain is connected to a supply line (a ground line also possible) of a power supply voltage V.sub.cc.
A plurality of memory cells shown in FIG. 21 are used and arranged in the form of an array, memory cells of each column are connected to the identical write bit line WBL and read bit line RBL, the gates of the write transistors Q1 of the memory cells of each row are connected to the identical write word line WWL, the capacitors C1 are connected to the identical read word line RWL, and thus a DRAM type semiconductor memory can be configured.
In the semiconductor memory, the write word line WWL and the read word line RWL are driven by the word line drive circuit. A write data buffer is connected to the write bit line WBL, a sense amplifier is connected to the read bit line RBL, and at the time of a read operation, the read bit line voltage of each is detected by the sense amplifier, whereby the data stored in the selected memory cell is read out.
Below, an explanation will be made of the read and write operations in the memory cell shown in FIG. 21 by referring to FIGS. 22A to 22C and FIGS. 23A to 23D.
FIGS. 22A to 22C are timing charts of the operation at the time of a read operation of the memory cell shown in FIG. 21. Before the read operation, as shown in FIG. 22C, first, each read bit line RBL is discharged to the low level, for example, a ground potential, and held in a floating state. Thereafter, a read voltage of the high level is applied to the read word line RWL as shown in FIG. 22A. By this, the read transistor Q2 is turned on or off corresponding to the storage data of the memory cell connected to the read word line RWL. For example, the read transistor Q2 of the memory cell holding the data "1" is turned on, and conversely the read transistor Q2 of the memory cell holding the data "0" maintains the off state. When the read transistor Q2 is turned on, the read bit line RBL is charged by the power supply voltage V.sub.cc and shifts to the high level. On the other hand, in a memory cell where the read transistor Q2 is off, the potential of the read bit line RBL does not change, and the low level after the discharge is maintained.
By the sense amplifier connected to the read bit line RBL, the potential difference of the read bit line RBL is detected, and the storage data of each memory cell is read out.
FIGS. 23A to 23D are timing charts showing the operation at the time of a write operation of the memory cell shown in FIG. 21. As shown in FIG. 23C, first, a voltage corresponding to the write data is supplied to the write bit line WBL. After the potential of the write bit line WBL is decided, a write voltage of the high level is supplied to the write word line WWL, whereby the write transistor Q1 is turned on, and the held voltage (or a voltage corresponding to the held voltage) of the write bit line WBL is transmitted to the storage node SN. Thereafter, when the write word line WWL shifts to the low level and the write transistor Q1 is turned off, the storage node SN exhibits a floating state, and the signal voltage is held at the storage node SN.
In a refresh operation, the read and write operations mentioned above are sequentially executed. By the read operation, the voltage of the read bit line RBL is set corresponding to the storage data of the memory cell. Thereafter, corresponding to the voltage of the read bit line RBL, for example by a refresh control circuit, the voltage of the write bit line WBL is set, and the voltage is written into the storage node SN again through the write transistor Q1.
The stored charge of a memory cell decreases along with the elapse of time mainly as an off leak current or the like of the write transistor Q1, but by periodically executing this refresh operation, the stored information can be restored before discrimination becomes impossible.
In a 2-transistor and 1-capacitor type gain cell having such a circuit configuration, as the capacitor structure in the memory cell, there is an MOS capacity type using an impurity region of the semiconductor substrate as a lower electrode. Further, there is a stack type forming an upper electrode and a lower electrode above the transistors Q1 and Q2 together with the interconnection and sandwiching a dielectric film between the electrodes in the middle of the formation. Further, there exists a floating gate type with the read transistor Q2 given a floating gate structure, connecting that floating gate as the storage node SN to the source or drain of the write transistor, and utilizing a capacitor inside the transistor Q2 formed by using the floating gate and the control gate (read word line RWL) insulated and isolated by an insulating film between gates as the electrodes for boosting the storage node voltage at the time of a read operation.
Summarizing the problems to be solved by the invention, however, in all gain cells, the drain of the read transistor Q2 must be connected to the supply line (or the ground line) of the power supply voltage V.sub.cc, therefore it was necessary to secure the interconnection region of that voltage supply line inside the memory cell. Further, when the voltage supply line is formed from an upper interconnection, a contact for connecting the read transistor to the voltage supply line must be formed. Further, two bit lines for writing and reading were required for each memory cell, so a large space became necessary in order to arrange the bit lines or form a bit contact.
Further, particularly in the MOS capacity type, the contact for connecting the semiconductor impurity region as the lower electrode of the capacitor to the gate electrode of the transistor became one of the factors behind the increase of the cell area. As a structure for making the contact unnecessary, it has been proposed to employ a TFT type as the read transistor and form the read transistor and capacitor in the upper layer of the write transistor ("A New SOI DRAM Gain Cell for Mbit DRAM's", H. Shichijo et al., Extended Abstracts of the 16th Conference on Solld State Device and Materials, A-7-3, 1984, pp. 265-268). In this memory cell, however, a disadvantage occurs that the formation of the TFT type transistor complicates the manufacturing step.
In the stack type, a multilayer interconnection structure for forming the capacitor electrode was necessary, and the capacitor dielectric film had to be separately formed from the inter-layer insulating film between interconnections since it had to be relatively thin, so it was necessary to add a manufacturing step for this purpose.
In the floating gate type, the gate structure of the read transistor was special and complex, so the match of the manufacturing process with the write transistors and other, for example, logic gate transistors was poor.
As described above, in the 2-transistor and 1-capacitor type gain cell of the related art, there was the problem that an increase of the memory cell area or an increase of the number of manufacturing steps could not be avoided.